1. Technical Field
The present invention relates to a substrate and a semiconductor device.
2. Related Art
A semiconductor element and an external electronic circuit substrate such as a mother board are connected generally as described below. First, the semiconductor element is mounted on an interposer such as printed substrate, and the product is then made up to a package in a form of LGA (land grid array) having flat electrode pads arranged on one surface of the interposer, BGA (ball grid array) further having solder balls disposed on the similar flat electrode pads, or the like. The package is then electrically connected to the external electronic circuit substrate such as the mother board, while placing a solder paste in between.
The flat electrode pad herein is configured by a portion of an interconnect pattern formed on one surface of the interposer, and exposed out from an opening of a solder resist layer formed further on the interconnect pattern. The configurations herein may be classified into those of solder mask defined (SMD) type in which each opening of the solder resist layer is smaller than each pad, so that the geometry of exposed area is defined by the solder resist layer; and those of non-solder mask defined (NSMD) type in which each opening of the solder resist layer is larger than each pad.
Japanese Laid-Open Patent Publication No. 2005-051240 describes a semiconductor device which adopts a solder ball land structure in which the SMD structure and the NSMD structure are combined. In a plurality of solder ball lands described in this document, a first peripheral portion of each land having the SMD structure is directed towards the center of the surface for mounting the solder balls, whereas a second peripheral portion of each land having the NSMD structure is reversely directed away from the center of the surface for mounting the solder balls. By virtue of the configuration, adhesion between the solder balls and the surface for mounting the same is reportedly more tightened, even if the surface for mounting the solder balls typically in a BGA semiconductor package should warp.
Japanese Laid-Open Patent Publication No. 2007-005452 describes a semiconductor device having an external connection terminal portion where the lands (pads) of a semiconductor package (semiconductor device) are connected to external connection terminals. In the external connection terminal portion, corner portions of each land are configured to have the SMD structure in which the surface of the land and the inner circumferential edge of each opening of an insulating film are brought into contact, and the middle portion of the outer edge of each land positioned between every adjacent pair of the corner portions are configured to have the NSMD structure in which a gap is formed between the outer edge of the land and the inner circumferential edge of each opening of the insulating film. In this configuration, a land extraction interconnect is formed at one corner of the land covered with the insulating film, and the SMD-structured portions and the NSMD-structured portions are alternately disposed at three or more positions.
By virtue of this configuration, the substrate interconnect extended from the land is reportedly prevented from being disconnected due to thermal stress ascribable to difference in thermal expansion coefficient between the semiconductor package and the mounting substrate (electronic circuit substrate).